1. Field of the Invention
The invention relates to an electronic device having storage retention capabilities and designed for use in, for example, a program memory of a data processing system.
2. State of the Prior Art
Memory field effect transistors (FETs) with storage retention capabilities and provided with a floating gate completely surrounded by an insulator have been disclosed in a great number of publications. A summary is given below of the properties of such memory FETs known in the prior art.
Memory FETs are programmable by means of the avalanche effect (cf. Solid-State Electronics 17 (1974), pp. 517-529) that is, in such memory FETs the floating gate is charged with carriers that are heated, or have relatively greater energy levels, as a result of the avalanche breakdown at the interface between drain and substrate, upon the breakdown of this otherwise non-conducting p-n junction. Due to their increased energy, these carriers can pass through the insulator, particularly if a voltage accelerating them is applied between the substrate and the floating gate. For example, FIG. 1 of U.S. Pat. No. 3,660,819, shows that such memory FETs with a floating gate 14 may also have a controllable charging gate 18 that acts capacitively on the floating gate 14. This influences the potential of the floating gate 14 and, hence, the drain to source current. Such memory FETs with a floating gate and controllable charging gate have been disclosed in a great number of other publications.
The carriers that are heated as a result of avalanche breakdown and injected into the floating gate may be electrons or holes. As is generally known, in n-channel memory FETs these carriers are holes, and in p-channel memory FETs they are electons (see the prior art cited hereinabove). Thus, the charge carriers charging the gate and heated by means of the avalanche effect have the polarity of the monority carriers in the drain.
Hence, in conventional memory FETs, the floating gate is charged negatively if it is a p-channel memory FET, but positively if it is a n-channel memory FET. Thus, the floating gates of both types of memory FETs charged as a result of avalanche breakdown always switch the relevent FET to its conducting state. This is due to the fact that the floating gate, regardless of the type of channel, will always exert such an infuence on the substrate region between drain and source by means of the injected charges, through electrostatic induction, that, compared with uncharged floating gates, the drain to source current is not inhibited, but stimulated. Thus, the injected charges exert such an influence on said substrate region that, through electrostatic induction, free charges are accumulated therein having the same polarity as the majority carriers in drain and source.
Accordingly, enhancement-mode FETs have been employed in the prior art as memory FETs, because only in such a FET is the resistance between source and drain in the non-program mode, that is, with the floating gate in uncharged condition, very high and in the program mode very low by comparison. Thus, the ratio of these two resistances is very high.
This phenomenon is illustrated in FIG. 7 herein, which is a graph of the dependence of the drain to source current I-DS on the charging gate/source voltage U-G2 of a conventional n-channel memory FET (cf. FIGS. 2 and 4 of IEEE Journal of Solid State Circuits SC7, No. 5, October 1972, pp. 369- 375). The curve GO in FIG. 7 applies to an uncharged floating gate of an enhancement-type FET and the curve G1 applies to a floating gate of the same FET charged by avalanche breakdown. By charging the floating gate (see 1 in FIG. 7), the conventional memory FET conducts current even if U-G2=0. Thus, after programming, the enhancement-type FET has the characteristics of a depletion-type FET with respect to its charging gate G2. Only after quenching, i.e., after discharging the floating gate, does the resistance of the memory FET for U-G2=0 increase again, since in that case the curve G0 can again be applied more or less accurately to the FET. Thus, the FET resumes its enhancement-type characteristics with respect to its charging gate G2.
If, instead, the conventional memory FET were equipped with a depletion-type channel, the floating gate charged during an avalanche breakdown condition would make the resistance of the existing channel still lower than it already is when the floating gate is the non-programmable mode. This, too, is illustrated in FIG. 7. The curve G1 shows the dependence of the drain to source current I-DS on the charging gate-source voltage U-G2 in the case of a N-channel depeletion-type memory FET in which the floating gate is in the non-program mode. When the floating gate of said FET is charged by avalanche breakdown, the curve G2 expresses the dependence of the drain to source current I-DS on the floating gate-source voltage U-G2. Due to the charging of the floating gate of the FET (see 1' in FIG. 2), that is, with the floating gate in the program mode, the FET conducts current if U-G2=0. Thus, in this mode, as in the unprogrammed mode, the depletion-type FET has depletion-type properties with respect to its charging gate G2. The conductivity of the memory FET is only insignificantly increased as a result of the programming, viz. by the factor 2, as soon as the depletion-type FET is programmaed by avalanche breakdown. This is illustrated in FIG. 7 by the intersection of the curve G2 with the I-DS axis.
Therefore, the ratio of the resistance between drain and source in the non-program mode to the resistance between drain and source in the program mode is much worse than in the case of the enhancement-type memory FET. Hence, only enhancement-type memory FETs have been employed in the prior art.
As is generally known, memory FETs with a floating gate can be quenched by optical means (see the prior art cited hereinabove, e.g., by illumination with ultraviolet light). Due to the irradiation, holes or electrons can be heated such that they pass through the insulator, discharging the floating gate.
Another method for quenching such memory FETs having a floating gate by electrical means is known. To do this, the charged floating gate of a first memory FET is later discharged with charges having an opposite polarity by means of a second avalanche breakdown produced in a second memory FET connected in parallel to the first memory FET (FIGS. 1 and 4 with accompanying description in the IEEE publication cited above). To achieve this, the memory FET simulates a parallel connection of a p-channel memory FET and a n-channel FET with a single common floating gate, and this device is referred to as the two-junction type (FIG. 6 herein). Similarly, said two-junction type, as shown in FIG. 1, has two different p-n junctions which optionally can be charged for breakdown in order to generate heated electrons or holes. In the non-program mode (see FIG. 4 of the referenced IEEE publication "as grown"), the two-junction type corresponds to an enhancement-type memory FET and, thus, is nonconducting if no voltage is applied to its floating gate. By means of the first avalanche breakdown the two-junction type is switched to the program mode, i.e., to its conducting state (see "1" state in FIG. 4 of the IEEE publication) by electrons injected onto the floating gate. By means of the second avalanche breakdown the two-junction type is discharged again by the holes (see "0" in said FIG. 4 of the IEEE publication).
Thus, in the non-program mode, all these conventional FETs are enchancement-type FETs with respect to their floating gates. However, in the program mode they always behave like depletion-type FETs, as far as their floating gates are concerned. Since the discharging usually does not occur without certain faults, there remain certain residual charges on the floating gate or in traps of the insulator between floating gate and substrate so that, after discharge, the two-junction type does not exhibit exactly the characteristics that existed prior to programming (see the spreads of the points of measurement in FIGS. 4 and 5 of the IEE publication). Nevertheless, after discharge the two-junction type behaves, as before, like an enhancement-type FET which, after reprogramming, is again conducting like a depletion-type FET.
These faults occurring during the electric quenching of memory FETs also occur in a conventional electrically quenchable FET having a channel length of about 10 micrometers and a resistivity of the p-substrate of about 10 ohm-cm and a normal structure of the drain and source (see FIGS. 2 and 5 of the above mentioned IEE publication). In this case, an n-channel memory FET is involved with an insulated floating gate G1 and an externally controlled floating gate G2. As is normal in prior art structures, the memory FET is of the enhacement type and in the non-program mode. Accordingly, after fabrication but prior to programming (see the "as grown" curve in FIG. 5 of the IEEE publication), the FET nonconducting when the floating gate G2 is free of potential. The memory FET is programmed by avalanche injection of holes and, thus, as is customary in presently known techniques, switched to its conducting state (see "1" in FIG. 5 of the IEEE publication). Thus, as a result of the programming, the enhancement-type memory FET assumes the characteristics of a depletion-type FET with respect to its floating gate. In this regard the memory FET is not different from other prior art n-channel memory FETs with a floating gate.
However, the quenching is not effected by electrical means nor with the aid of a second avalanche breakdown, as is the case with the two-junction type shown in the FIG. 1 cited above. The quenching of the positively charged floating gate shown in FIG. 5 occurs by electrical means with the aid of a very rare physical effect, only described by these authors, and referred to as "channel injection". As described in the above referenced IEEE publication, the memory FET is switched at its floating gate to a virtually nonconducting state, so that in a small region of the channel a substantially smaller charge carrier density prevails than in the other regions of the channel. In the low-charge region there arise fairly high longitudinal field strengths between source and drain relative to the remaining higher-charge regions of the channel. The free flowing in the low-charge region are thus heated up to a greater degree than in the remaining channel regions. If the charges are sufficiently hot in the low-charge region, they can pass through the insulation and charge the floating gate G1. The channel-injection induced charges passing through the insulation are in this case electrons which are used to inversely charge the floating gate of the n-channel memory FET. Thus, for quenching purpose, the floating gate is provided with electrons generated by channel injection, and for programming purposes with holes generated by avalanche breakdown.
After the discharge produced by the channel injection, which according to said publication, occurs very slowly, the memory FET has approximately the same enhancement-type characteristics as prior to programming. Thus, if the floating gate is free of potential, the source and drain region is more or less nonconducting. Here, too, small faults are normally noticeable after discharge, because residual charges remain on the floating gate or in traps of the insulator between the floating gate and the substrate. As a result of the residual charges, the memory FET, after quenching, has not exactly the same characteristics as prior to programming.
The various prior art memory FETs with an insulated floating gate are thus so programmed, using the avalanche breakdown, that they are switched to the conducting state, that is, that the charging of the floating gate acts on the source and drain region through induction in such a manner that it stimulates the drain to source current. As a result of the programming, the memory FET assumes depletion-type characteristics. Optical and two different electrical quenching methods have been disclosed, whereby the electrical quenching is effected either by means of a second memory FET or by using the channel injection.